The present disclosure related generally to the physical design and verification of three-dimensional (3D) integrated circuits.
A 3D integrated circuit (3D IC) includes a semiconductor a device with two or more layers of active electronic components integrated (e.g., vertically stacked and connected) to form an integrated circuit. Various forms of 3D IC technology are currently being developed including die-on-die stacking, die-on-wafer stacking, and wafer-on-wafer stacking. In 3D IC technology electronic components (e.g., integrated circuits) are built on two or more substrates and packaged to form a single integrated circuit. The electronic components are aligned and bonded together, either after dicing into singulated die or while in wafer form (which may then be subsequently diced). Vertical connections are made between the electronic components such as through the use of through-silicon vias (TSVs). The stacked die may be then packaged such that I/Os can provide connection to the 3D IC.
3D IC technology is desirable in that it allows greater functionality to be provided in a smaller footprint and with increased speed (for example, a shorter vertical connections may provide for decreased delay). However, 3D IC technology also includes challenges. Each electronic component or device (e.g., die) itself includes complicated design features. The interaction of the stacked die create even greater design challenges, which have not yet been addressed by designers, including CAD tool developers. Both the physical connections and the electrical connections between stacked devices must be made accurately and robustly made. An improved method of connection, and verification of such a connection is desired.